Minimising ATTiny ADC power consumptionPublished: April 17, 2017
Tags: adc attiny avr electronics hacking hardware low power
This post is a quick note on making full use of the power saving settings for the analog-to-digital converter in ATTiny chips. This is based on my experience tinkering with the ATTiny84 but I suspect that it applies pretty broadly across the family, including to the more popular ATTiny85.
The ADC is one of the most power hungry peripherals on these chips, and if you are trying to achieve an ultra low power sleep state for a battery- or solar-powered application its important to shut it down when its not in use. Somewhat confusingly, there are two options provided to facilitate this. You can disable the ADC by clearing the
ADEN bit in the
ADCSRA register (which, to my understanding, stops the ADC clock running but leaves the ADC powered up), but you can also actually power down the ADC by setting the
PRADC bit in the
PRR power reduction register (AVR libc provides convenience functions for doing this,
power_adc_enable()). Disabling the ADC seems to provide a much greater power saving than powering it down (i.e. the ADC consumes very little power when the clock is not running), but if you are really gunning for nanoamp consumption then to get maximum savings you should do both.
Basically all I'm writing this for is to emphasise the fact that when doing both of these things you need to pay attention to the order in which you do them for things to work as expected. The datasheet is almost explicit about this, saying "The ADC must be disabled before shut down" (i.e. write to
ADCSRA before you write to
PRR). What it doesn't say is that, when bringing the ADC back up, you need to do the reverse and restore power before enabling it (i.e. write to
PRR before you write to
ADCSRA). Arguably this is obvious, but its easy to overlook, especially if you do what I did: write your "power up" code by copying and pasting your "power down" code and reversing the bit setting/clearing logic without reversing the order of the lines. As far as I can tell, if you try to enable a powered down ADC, your write to
ADCSRA will simply be ignored. When you then power it up,
ADEN remains cleared, and any reads from
ADCL will simply return the value of the last successful conversion, making it look like your ADC is "stuck". So be careful!